The invention relates to communication and control topology for efficient testing of sets of devices.
Digital circuitry implemented in an integrated circuit can be complex, and may include specialized circuitry that supports testing of various devices on the fabricated chip. For example, a system-on-a-chip (SoC) may include a central processing unit (CPU), which may be a multi-core processor with multiple processor cores, in addition to various digital or analog devices that provide a variety of functionality used by, or operating alongside, the CPU. One type of circuitry that facilitates testing of devices is based on built-in self-test (BIST) and built-in self-repair (BISR) techniques. One way to provide access to signals propagating to or from circuitry being tested by such techniques is to use a “scan chain” (also called a “serial shift chain”) that uses a closed loop of nodes coupled to different devices. The nodes serially receive and forward information around the loop during a testing procedure. A standard known as “JTAG” (Joint Test Action Group) or more formally “1149.1 IEEE Standard for Test Access Port and Boundary-Scan Architecture,” has been used for testing printed circuit boards (PCBs) and integrated circuits (ICs). Typically, there are multiple boundary scan cells, each connected to a portion of the circuitry being tested. A chain of cells is formed with a cell being connected to two neighboring cells over a point-to-point multi-wire bus. This chain may be located at the boundary of a PCB or IC with cells also being connected to input/output (I/O) pins. Test information can be sent around the chain to test any device in the system from a single standardized interface.